The present invention relates, in general, to integrated circuit design, and in particular to a shrinkable integrated circuit design for circuits having both bipolar and CMOS circuit elements.
Integrated circuits take months or years to design, and due to advancements in process technology, the design may become obsolete soon after the design is complete. In the past, when new process technology allowed manufacturers to produce circuits with smaller dimensions, the integrated circuit had to be re-designed or redrawn to implement the smaller dimension. Often the redesign took several months. Circuit designs, or layouts, are usually done on a computer aided design (CAD) system, which processes a digital record of the layout. In order to reduce redesign time, CAD systems are used to arithmetically shrink the layout, also called scaling the design. While scaling works very well for some circuit elements, such as CMOS elements and passive components, it works poorly on others, such as bipolar elements. This is because parameter changes in CMOS elements and passive components are roughly linear with size, while bipolar elements change non-linearly. To take advantage of smaller dimensions in a bipolar circuit each transistor was redesigned, not simply scaled, and often times circuit changes were made to compensate for the parametric changes of the bipolar transistors. Scaleable circuits enjoy a longer product lifetime, and are more cost effective than non-scaleable circuits.
Recently, integrated circuits have become available having both CMOS and bipolar elements formed on a single shared substrate. These circuits are called BiCMOS circuits and comprise CMOS devices built in the substrate, and bipolar cells which are formed in areas which are isolated from the the CMOS devices. The boundary of the isolation area is usually spaced as near to an outside edge of the bipolar cell as possible, and the spacing is substantially uniform for each bipolar cell on a chip. The isolation spacing, which is the separation between the boundary of the isolation area and the outside edge of the bipolar cell, is a function of a minimum geometry drawn in the circuit, as well as peak voltage which is applied to the circuit. For example, minimum isolation spacing for three micron minimum geometry circuits is typically 12-15 microns, and isolation spacing for sub-micron minimum geometry is three to four microns. In general, the minimum isolation spacing is frequently about four to five times the minimum geometry of the circuit.
While large portions of BiCMOS circuits are scaleable, manufacturers have faced the same redesign problem with BiCMOS circuits as with bipolar circuits. Because many of the bipolar elements required redesign, not just scaling, the time delay to take advantage of new process technology was excessively long. Bipolar cells were redesigned to smaller geometries when possible, and when this was not possible, the surrounding isolation region and CMOS circuitry were redesigned to fit around the original bipolar cell.
Accordingly, it is an object of the present invention to provide a bipolar-CMOS circuit which is scaleable.
It is a further object of the present invention to provide a method for laying out a BiCMOS circuit which anticipates future process improvements.
It is another object of the present invention to provide a BiCMOS integrated circuit which can be scaled by a CAD system with minimal redesign.
It is a further object of the present invention to provide a faster method for shrinking BiCMOS integrated circuits.
It is a still further object of the present invention to provide a BiCMOS integrated circuit with a longer product lifetime.